The present invention relates to a semiconductor device and, more particularly, to a bipolar transistor and a method of manufacturing the same.
When a functional element such as a switching element is formed on a semiconductor substrate, the depth of the substrate occupied by the element is only 10 .mu.m from the substrate surface. Therefore, in many cases, the semiconductor substrate region remaining after formation of the element is preferably replaced with an insulating substrate in terms of the characteristics. For example, a semiconductor element on the insulating substrate is called SOS (Silicon On Sapphire) and is effective for a high speed and a high withstand voltage of the element. However, many defects are present in the SOS due to heteroepitaxially grown crystals, resulting in poor characteristics. For this reason, a method of fixing an element surface layer preformed on a semiconductor monocrystalline substrate to a first supporting substrate using an adhesive, forming the substrate thin by etching or the like, fixing the resultant surface to a second supporting substrate using an adhesive, and removing the first supporting substrate to expose the element surface is reported (Japan. J. Appl. Phys., Vol. 23, No. 10, pp. L 815, 1984). A semiconductor device manufactured in such a manner is shown in FIG. 1. In FIG. 1, reference numeral 1 denotes a semiconductor layer; 2, a bonding pad; 3, a protecting insulating film; 4, an adhesive layer; and 5, a supporting substrate. As shown in FIG. 1, the bonding pad and wirings exist on only one surface of the semiconductor device. Moreover, when a CMOS is formed in the manner described above, since the substrate region of the transistor is not connected to a constant power source but is floating, the operation margin is narrowed. Conventionally, in order to form an npn bipolar transistor, an n.sup.+ -type buried impurity layer is formed by an ion-implantation method in a region to serve as an element active region on a p-type silicon substrate to obtain a collector region, an n.sup.- -type layer is epitaxially grown on the collector region, a p-type base diffusion region is formed and an n.sup.+ -type emitter region is formed therein (IEEE, J. Solid-State Circuit, Vol. SC-16, No. 5, pp. 424-429, 1981).
FIG. 2 is a sectional view showing a conventional npn bipolar transistor. In FIG. 2, reference numeral 101 denotes a p-type silicon substrate; 102, an n.sup.+ -type buried impurity layer; 103, an n-type epitaxial layer; 104, a p-channel stopper region; 105, a field oxide film; 106, a base diffusion region; 107, an emitter contact region; 108, a collector contact region; 109, an interlayer insulating film; and 110, electrode wirings.
In such a bipolar transistor, the following two factors are required. First, in order to improve a switching rate of a transistor, the resistance of the conventional buried impurity layer 102 must be reduced. Second, an element isolation region must be reduced in area to obtain a high packing density. However, a conventional structure cannot satisfy these two requirements at the same time. More specifically, if the impurity concentration of an n.sup.+ -type buried impurity layer 102 is increased to decrease its resistance and an n-type epitaxial grown layer 103 is to be grown, an impurity doping called an autodoping tends to enter, so that an n-type epitaxial grown layer must be formed thick to obtain a low-concentration epitaxial surface. As a result, when a thick epitaxial film is isolated by a field oxide film 105, the amount of an oxide film which enters into a nitride film, i.e., the amount of bird's beak is increased, resulting in a large element isolation region. As described above, when a collector resistance is decreased to obtain a high-speed, a size required for element isolation is increased, thereby preventing a high element packing density. A transistor structure or a means which realizes a high speed and a high packing density of a bipolar transistor has not been reported yet.
In addition, in a conventional bipolar transistor, emitter, base, and collector regions are sequentially arranged in this order in a semiconductor layer surface. Since wiring electrodes are connected to respective regions, it is difficult to decrease the unit size of a transistor or is necessary to provide a margin for wiring regions so that respective wirings do not cross each other, thereby preventing a high element packing density.